1. Field of the Invention
The present invention relates to digital memory circuits and, more particularly, to digital memory circuits that provide a predetermined series of fixed digital data words.
2. State of the Art
In the field of digital signal processing, it is often necessary to generate cyclically-repeated, multi-bit constant sequences. Such sequences must be generated, for example, in digital filters of the finite impulse response (FIR) type. In those filters, each of a series of incoming data points x.sub.i is multiplied in turn by each of a series of constant coefficients A.sub.i, with the resulting series of products being added together. The generation of cyclically-repeated, multi-bit constant sequences is also necessary when computing Fast Fourier Transforms (FFT) as well as in other digital signal processing applications.
It is known to generate cyclically-repeated, multi-bit sequences by using a read only memory (ROM) in conjunction with an address generator. In such an arrangement, because storage and control are realized separately, it is difficult to realize a suitable constant generator in bit-slice form. The reason for such difficulties is that as the number of constants in the sequence increases, the number of ROM data locations increases linearly while the number of ROM address bits and hence the size of an address counter portion of the address generator increases only logarithmically. A single bit-slice size therefore cannot be used.